The present invention generally relates to a dynamic random access memory and a method of producing the same, and in particular to a structure of a cell composed of a transfer transistor and a charge storage capacitor and a method of forming the cell structure.
Currently, samples of dynamic random access memory devices (hereafter simply referred to as DRAM device) of 16 Mbits are available. As the integration density is increased, a size of the cell on a plane must be reduced. Generally, a reduction in the size of the cell leads to a reduction in capacitance of the charge storage capacity. Additionally, as the capacitance is reduced, a soft error arising from the incidence of an .alpha.-ray is increased. For this reason, it is desired to decrease the size of the charge storage capacitor on the plane without reducing the capacitance thereof.
For this requirement, stacked capacitor type DRAM devices have been proposed and realized. In a conventional stacked capacitor type DRAM device, one of a pair of electrodes of the storage capacitor is formed so as to have a three dimensional structure. The three dimensional structure of the electrode results in a 30-40 % increase in the capacitance of the storage capacitor, compared with a storage capacitor of two dimensional structure having the same size on the plane. However, an increase in the capacitance provided by the conventional three-dimensional electrode is not enough to fabricate a highly integrated DRAM device having a integration density of 16 Mbits or more.
It is also known that in order to increase the capacitance of the capacitor, a dielectric film included in the storage capacitor is made of a material of a high dielectric constant such as tantalum oxide (Ta.sub.2 O.sub.5). However, the use of Ta.sub.2 O.sub.5 causes an increased leak current passing through the insulating film, compared to a dielectric film made of silicon dioxide (SiO.sub.2) or silicon nitride (Si.sub.3 N.sub.4).
Trench type DRAM devices have also been proposed and realized in which a number of trenches are formed on a surface of a semiconductor substrate, and storage capacitors are formed into the trenches. For a 16Mbit-class DRAM device, it is difficult to separate neighboring storage capacitors from each other by a distance of less than approximately 0.5 [.mu.m]. Such an arrangement of the neighboring storage capacitors may cause an interference which occurs. In the interference, a charge stored in one of the neighboring storage capacitors is transferred to the other capacitor when a voltage is applied to the other capacitor, and therefore information is destroyed.
Yet another conventional DRAM device has been proposed in the Japanese Laid-Open Patent Publication No. 9154/1985. The publication discloses a storage capacitor having a multilayer structure, the elevational cross section of which has a comb shape.
However, the prior art disclosed in the above publication has the following disadvantages. Firstly, the transfer transistor and the charge storage capacitor are arranged side by side on the substrate. Therefore, a high integration density cannot be obtained. Secondly, a considerably increased capacitance of the storage capacitor of the publication cannot be obtained, because the storage capacitor has the comb-shaped cross section, that is, the storage electrode does not have the projections formed on all the side surfaces thereof.